Building Before the Demand: ASML’s Long-Term Semiconductor Bet

ASML’s Eindhoven expansion shows why semiconductor capacity, High-NA EUV and chip manufacturing must now be planned years before future demand arrives.
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Arthur Kellan

Editor-in-chief at Vireon Press, covering business and technology through the lens of strategy, efficiency, and real-world consequences.

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ASML’s new Eindhoven campus is being built for a semiconductor market that is still taking shape. The company this week broke ground on a site covering roughly 350,000 square metres and designed for up to 20,000 workplaces [1].

The more revealing detail is the timing. ASML is committing physical capacity years before the production volumes it is preparing for are fully visible. Cleanrooms, tooling capacity, suppliers and specialist labour cannot be added quickly once a new technology cycle is already underway.

That forces semiconductor companies to plan further ahead than the market itself. Waiting for clear commercial signals now means risking a structural deficit; physical infrastructure must be secured long before the next production cycle arrives.

High-NA Makes the Roadmap Physical

High-NA EUV adds another constraint: the next generation of chips has to fit the physical logic of the machines that will produce it. ASML’s EXE:5000 can print features at 8 nm resolution, allowing transistor densities 2.9 times higher than its current NXE systems. But the anamorphic optics behind that improvement cut the exposure field in half [2].

That trade-off becomes more important as data-center processors grow larger. A smaller field limits how much of a large die can be exposed at once, forcing chipmakers to rethink how those designs are patterned. ASML is already working with major manufacturers on larger masks that would allow High-NA systems to handle chips closer in size to today’s largest data-center processors; Reuters says a pilot line is planned for 2031, with high-volume use targeted for 2033 [3].

The implication reaches beyond lithography. Chip architecture and manufacturing equipment are starting to evolve together, years before either reaches full-scale production. The same pressure is already visible in AI infrastructure spending, where companies are committing enormous sums before the full return profile is clear. In semiconductors, the physical boundaries of the production system are becoming part of the design brief itself.

Physical Foundations Outrun Digital Agility

The semiconductor industry is now exposing a mismatch that sits beneath the entire digital economy. Demand for computing can surge within months, but the equipment needed to produce that computing power cannot follow at the same speed.

ASML’s own order book shows how far ahead that physical layer is already being scheduled. In its second-quarter results, the company said customer commitments were giving it greater visibility into longer-term demand. It plans to increase low-NA EUV capacity by about 30% in 2027 from a 2026 base of roughly 65 systems, while studying another 30% increase for 2028 [4]. ASML later told investors that 2027 capacity was already close to fully covered by orders, with a significant number of 2028 orders also in hand.

Those numbers are more revealing than the quarter’s €9.3 billion in sales. They show that equipment capacity is being allocated before many of the chips it will produce have reached the market. Capital deployment is now decoupled from short-term tech earnings.

That creates a hard boundary for the faster-moving parts of the industry. Software models can be replaced, workloads can shift and data-center investment can accelerate quickly. Lithography systems, cleanrooms, precision optics and the supplier network behind them cannot expand at the same pace. The speed of the next computing cycle will increasingly depend on how much of that physical base was prepared before demand reached it.

The Execution Risk of Timing

The deeper change is that semiconductor competition is becoming less sequential. Chip design, equipment procurement, supplier capacity and factory investment increasingly have to move together.

That changes where execution risk appears. A stronger chip architecture is not enough if the production system behind it is late, while excess capacity can be just as costly if technology adoption moves more slowly than expected. The advantage lies in matching several long investment cycles to a market that still changes quickly, particularly as capital costs make mistakes in timing and scale more expensive.

For chipmakers and equipment suppliers, forecasting is becoming part of manufacturing strategy itself. Ultimately, the modern tech economy faces a structural mismatch: digital models move instantly, but the industrial foundation underneath them scales over years. The winners of the next cycle are being decided by who accepts that constraint today.

Sources:

[1] ASML — ASML begins construction of new Eindhoven campus, strengthening its presence in the Brainport region

[2] ASML — TWINSCAN EXE:5000 — EUV lithography systems

[3] Reuters — ASML to work with major chipmakers to use latest tools for larger chips

[4] ASML — ASML reports €9.3 billion total net sales and €2.9 billion net income in Q2 2026

Editor-in-chief at Vireon Press, covering business and technology through the lens of strategy, efficiency, and real-world consequences.

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